1. Field of the Invention
The present invention relates to an emitter switching configuration and, more specifically, the invention relates to an emitter switching configuration comprising at least a bipolar transistor and a MOS transistor having a common conduction terminal and to an integrated structure effective to implement the emitter switching configuration to be integrated on a single chip.
2. Description of the Related Art
As it is well known, in applications requiring a high switching speed of a switch implemented by means of a bipolar transistor, this bipolar transistor is associated with a MOS transistor, inserted in series with an emitter terminal of the bipolar transistor in the configuration commonly known as emitter switching, schematically shown in FIG. 1 and globally indicated with 1.
The emitter switching configuration 1 essentially has a bipolar transistor T1 with a collector terminal C1, an emitter terminal E1, and a control or base terminal B1. The emitter terminal E1 of transistor T1 is connected to a drain terminal D1 of a MOS transistor M1 having also a source terminal S1 and a control or gate terminal G1.
Advantageously, by using the emitter switching configuration 1, the lock of the MOS transistor M1 allows transistor T1 to be rapidly turned off since it cuts the emitter current thereof.
Moreover the emitter switching configuration 1 can be integrated in a single chip, forming the MOS transistor M1 in a diffusion related to the emitter terminal E1 of the bipolar transistor T1. The MOS transistor M1 will be N or P-channel according to whether the emitter terminal E1 is of the N or P type.
The MOS transistor drain terminal D1 therefore corresponds to the emitter terminal E1 of the bipolar transistor T1. The so-formed MOS transistor M1 is particularly a VDMOS transistor, i.e., a double-diffusion vertical MOS transistor.
Being the emitter terminal region of a bipolar transistor an heavily doped semiconductor region, in order to integrate a MOS transistor therein a particular monolithic structure is to be used, such as the one shown in FIG. 2.
Particularly, the monolithic structure 2 has a semiconductor substrate 21 of a first conductivity type, for example of the N type, effective to form the collector terminal C1 of the bipolar transistor T1.
A first buried layer 22 of a second conductivity type, for example of the P type, is formed on the substrate 21 and a second buried layer 23 of the first conductivity type.
The monolithic structure 2 thus has an epitaxial layer 24 of the first conductivity type covering the first 22 and second 23 buried layers.
A double-diffusion region of the second conductivity type 25 is formed in the epitaxial layer 24, corresponding to body or bulk regions of the MOS transistor M1, wherein a high-concentration double-diffusion region 26 of the first conductivity type is formed, corresponding to the source region S1 of the MOS transistor M1. The monolithic structure 2 also includes polysilicon structures 27 effective to form the gate terminal G1 of the MOS transistor M1.
The monolithic structure 2 is completed by a contact structure 28A effective to form the source terminal S1 of the MOS transistor M1, as well as a contact structure 28B effective to form the base terminal B1 of the bipolar transistor T1 and in contact with the first buried layer 22 by means of convenient wells 29 of the second conductivity type.
It is worth noting that in the monolithic structure 2 the buried layers 22 and 23 form the emitter and base regions of the bipolar transistor T1, these regions being buried by means of a higher-resistivity epitaxial layer 24 wherein the body regions 25 of the MOS transistor M1 are diffused. Moreover, the epitaxial layer 24 is the drain region of the MOS transistor M1.
The emitter switching configuration 1 being integrated by means of the monolithic structure 2 is driven as an insulated gate device, essentially of the power MOS type. However, the emitter switching configuration 1 has advantageously a lower resistance in conduction conditions than known power MOS devices. This advantage is further increased if the inverse voltage value to be undergone by the device increases, i.e., the voltage rating.
Particularly, the monolithically-integrated emitter switching configuration 1 has a low-voltage MOS transistor M1, and it has thus a low conduction resistance value Ron. Besides, in lock conditions, the entire inverse voltage applied to the emitter switching configuration 1 is supported by the base-collector junction of the bipolar transistor T1 without affecting thus the body-drain junction of the MOS transistor M1.
The body-drain junction of the MOS transistor M1 is stressed only in the turn-off step. In fact, in the turn-off step, the entire current of the bipolar transistor T1 collector terminal C1, being no more allowed to flow through the emitter terminal E1 thereof which is locked by the MOS transistor M1 turn-off, is obliged to leave the base terminal B1 of the bipolar transistor T1 by passing thus through the first buried layer 22 and wells 29. The body-drain junction of the MOS transistor M1 thus undergoes an inverse voltage VMOS given by:VMOS=Ic*RB
where RB is the resistance of the second buried layer 22 and of the wells 29 and Ic is the current to be switched.
It is thus evident that, if the value of the current Ic to be switched is too high, the body-drain junction of the MOS transistor M1 can breakdown, interrupting thus the bipolar transistor T1 turn-off step. The latter, undergoing high inverse voltages with simultaneous high current flowing, can be thus seriously damaged or even destroyed.
Definitely, the highest current Ic value, or current capability, which can be switched by the bipolar transistor T1 in the emitter switching configuration depends on the breakdown voltage value of the MOS transistor M1.
In other words, the increase in the “current capability” of the bipolar transistor T1 is obtained at the detriment of the conduction resistance Ron of the MOS transistor M1 and thus of the whole monolithic structure 2 in the emitter switching configuration.